Liquid crystal display and method of charging/discharging pixels of a liquid crystal display

ABSTRACT

A liquid crystal display includes a liquid crystal panel, a source driving circuit, a timing controller, and a gate driving circuit. The source driving circuit converts frame data into a plurality of data voltages, and charges/discharges a first data line according to a data voltage of the plurality of data voltages. The gate driving circuit enables a gate line corresponding to the data voltage. The timing controller sequentially enables a plurality of switch enable lines corresponding to the gate line. A plurality of pixel switches are turned on according to the enabled gate line. A data line switch is turned on according to an enabled switch enable line. The data voltage charges/discharges a corresponding pixel through the turned-on data line switch and one of the turned-on pixel switches.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.14/561,227, filed Dec. 5, 2014, now allowed, which is a divisional ofU.S. patent application Ser. No. 13/450,430 filed Apr. 18, 2012, nowabandoned, which claims priority to Taiwan Patent Application No.100117917, filed May 23, 2011, each of which is incorporated herein byreference in its entirety.

FIELD OF THE INVENTION

The present invention relates to liquid crystal displays and methods ofcharging pixels of liquid crystal displays, and particularly to a liquidcrystal display and method of charging pixels thereof that utilizeenable signals of two partially-overlapping consecutive gate lines andsequentially-enabled switch enable lines to extend pixel charging time.

BACKGROUND OF THE INVENTION

Please refer to FIG. 1A and FIG. 1B. FIG. 1A is a diagram illustrating aliquid crystal display (LCD) 100 capable of reducing first data lines ofa source driving circuit. FIG. 1B is a diagram illustrating timing ofoperating gate lines G1, G2, G3 and switch enable lines SW1, SW2, SW3 ofthe prior art. As shown in FIG. 1A, first data line FD1 of sourcedriving circuit corresponds to second data lines SD11, SD12, SD13, andfirst data line FD2 of source driving circuit corresponds to second datalines SD21, SD22, SD23. Thus, liquid crystal display 100 uses switchenable lines SW1, SW2, SW3 and a plurality of data line switches DS11,DS12, DS13, DS21, DS22, DS23 to reduce number of first data lines ofsource driving circuit. As shown in FIG. 1B, when gate line G1 isenabled and switch enable lines SW1 are enabled, data voltage of firstdata line FD1 charges second data line SD11 through data line switchesDS11, and second data line SD11 charges pixel P11 through pixel switchPW11. Likewise, when gate line G1 is enabled and switch enable line SW2is also enabled, data voltage of first data line FD1 charges second dataline SD12 through data line switch DS12, and second data line SD12charges pixel P12 through pixel switch PW12. When gate line G1 isenabled and switch enable line SW3 is also enabled, data voltage offirst data line FD1 charges second data line SD13 through data lineswitches DS13, and second data line SD13 charges pixel P13 through pixelswitch PW13. As shown in FIG. 1B, because switch enable lines SW1, SW2,SW3 are enabled sequentially, charge time of pixel P11is interval T1,charge time of pixel P12 is interval T2, charge time of pixel P13 isinterval T3, where T1>T2>T3, which causes charge rates of pixel P11,pixel P12, and pixel P13 to be different. Thus, liquid crystal display100 exhibits color distortion.

SUMMARY OF THE INVENTION

According to an embodiment, a liquid crystal display (LCD) comprises anLCD panel, a source driving circuit, a gate driving circuit, and atiming controller. The LCD panel comprises a plurality of pixels. Eachpixel of the plurality of pixels is coupled to a corresponding pixelswitch. The source driving circuit is for converting image data into aplurality of data voltages and enabling M first data lines. M is apositive integer. Each first data line of the M first data linescorresponds to a plurality of data line switches, and the first dataline charges/discharges according to a data voltage corresponding to thefirst data line. Each data line switch of the plurality of data lineswitches corresponds to one second data line and one switch enable lineof a plurality of switch enable lines. The gate driving circuit is forenabling N gate lines, where N is a positive integer. The timingcontroller is for enabling the plurality of switch enable lines. Enablesignals of a gate line and a next gate line corresponding to the gateline are partially overlapping.

According to an embodiment, a method of charging/discharging pixels of aliquid crystal display is provided. The liquid crystal display comprisesan LCD panel, a plurality of switch enable lines, a source drivingcircuit and a gate driving circuit. The method comprises convertingimage data into a plurality of data voltages, charging/discharging afirst data line corresponding to a data voltage of the plurality of datavoltages according to the data voltage, enabling a gate linecorresponding to the first data line of a plurality of gate lines,sequentially enabling all switch enable lines corresponding to the gateline of a plurality of switch enable lines, turning on a plurality ofpixel switches corresponding to a gate line that is asserted accordingto the gate line, turning on a data line switch corresponding to switchenable lines that are asserted according to the switch enable lines, thedata voltage charging/discharging a second data line corresponding to adata line switch that is turned on through the data line switch, and thesecond data line that is being charged/discharged charging/discharging apixel corresponding to a pixel switch that is turned on of the pluralityof pixel switches through the pixel switch. Enable signals of the gateline and a next gate line corresponding to the gate line are partiallyoverlapping.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a diagram illustrating a liquid crystal display capable ofreducing first data lines of a source driving circuit.

FIG. 1B is a diagram illustrating timing of operating gate lines andswitch enable lines of the prior art.

FIG. 2A is a diagram illustrating liquid crystal display.

FIG. 2B is a diagram illustrating timing of operations of liquid crystaldisplay.

FIG. 3A is a diagram illustrating a liquid crystal display according toan embodiment.

FIG. 3B is a diagram illustrating operation timings of liquid crystaldisplay.

FIG. 4 is a diagram of liquid crystal display according to anembodiment.

FIG. 5 is a flowchart of a method of charging/discharging pixels of aliquid crystal display according to an embodiment.

DETAILED DESCRIPTION OF THE INVENTION

Please refer to FIG. 2A and FIG. 2B. FIG. 2A is a diagram illustratingliquid crystal display 200, and FIG. 2B is a diagram illustrating timingof operations of liquid crystal display 200. Liquid crystal display 200comprises LCD panel 202, source driving circuit 204, gate drivingcircuit 206, and timing controller 208. LCD panel 202 comprises aplurality of pixels, and each pixel of the plurality of pixels iscoupled to a corresponding pixel switch, where each pixel switch is anN-type thin-film transistor or P-type thin-film transistor. Sourcedriving circuit 204 is used for converting image data to a plurality ofdata voltages and enabling M first data lines FD1-FDM, where M is apositive integer. Each first data line of M first data lines FD1-FDMcorresponds to a plurality of data line switches, and each first dataline is charged/discharged according to a corresponding data voltage,where each data line switch corresponds to one second data line and oneswitch enable line of three switch enable lines SW1-SW3, and each dataline switch is either an N-type thin-film transistor or P-type thin-filmtransistor. For example, first data line FD1 corresponds to three dataline switches DS11, DS12, DS13, first data line FD2 corresponds to threedata line switches DS21, DS22, DS23, data line switch DS11 correspondsto second data line SD11 and switch enable line SW1, data line switchDS12 corresponds to second data line SD12 and switch enable line SW2,and data line switch DS13 corresponds to second data line SD13 andswitch enable line SW3. Gate driving circuit 206 is used for enabling Ngate lines G1-GN, where N is a positive integer, and enable signals oftwo neighboring gate lines are partially overlapping. Timing controller208 is for sequentially enabling a plurality of switch enable linesSW1-SW3.

As shown in FIG. 2B, while gate line G1 is enabled, and source drivingcircuit 204 charges/discharges first data line FD1 according tocorresponding data voltage, gate line G2 is pre-enabled, namely enablesignal of gate line G1 and enable signal of gate line G2 partiallyoverlap. Thus, when switch enable line SW1, gate line G1 and gate lineG2 are both enabled (period T1 of FIG. 2B), first data line FD1charges/discharges second data line SD11 through turned on data lineswitches DS11 according to corresponding data voltage, and second dataline SD11 charges/discharges pixel Pill through turned on pixel switchPW111 according to corresponding data voltage. At this time, becausegate line G2 is also enabled, second data line SD11 alsocharges/discharges pixel P211 through turned on pixel switch PW211according to corresponding data voltage. Likewise, in period T2 of FIG.2B, first data line FD1 charges/discharges second data line SD12 throughturned on data line switch DS12 according to corresponding data voltage,and second data line SD12 charges/discharges pixel P112 through turnedon pixel switch PW112 according to corresponding data voltage. At thistime, because gate line G2 is also enabled, second data line SD12 alsocharges/discharges pixel P212 according to corresponding data voltagethrough turned on pixel switch PW212. Likewise, in period T3 of FIG. 2B,first data line FD1 charges/discharges second data line SD13 throughturned on data line switch DS13 according to corresponding data voltage,and second data line SD13 charges/discharges pixel P113 through turnedon pixel switch PW113 according to corresponding data voltage. At thistime, because gate line G2 is also enabled, second data line SD13 alsocharges/discharges pixel P213 through turned on pixel switch PW213according to corresponding data voltage. As shown in FIG. 2B, polaritiesof pixel Pill and pixel P211 are the same, polarities of pixel P112 andpixel P212 are the same, and polarities of pixel P113 and pixel P213 arethe same. Thus, pixel P211, pixel P212 and pixel P213 have already beenpre-charged/pre-discharged by data voltages corresponding to pixel P111,pixel P112, and pixel P113 prior to being charged by corresponding datavoltages. Thus, liquid crystal display 200 may increase charging rate ofpixel P211, pixel P212 and pixel P213. Additionally, operation timingsof other gate lines liquid crystal display 200 are similar to those ofgate line G1 and gate line G2, and are not described again here.

Please refer to FIG. 3A and FIG. 3B. FIG. 3A is a diagram illustrating aliquid crystal display 300 according to an embodiment. FIG. 3B is adiagram illustrating operation timings of liquid crystal display 300.Liquid crystal display 300 comprises LCD panel 302, source drivingcircuit 304, gate driving circuit 306, timing controller 308. LCD panel302 comprises a plurality of pixels, where each pixel of the pluralityof pixels is coupled to a corresponding pixel switch, and each pixelswitch is an N-type thin-film transistor or a P-type thin-filmtransistor. Additionally, each pixel switch has a first terminal coupledto a corresponding pixel, a second terminal coupled to a correspondinggate line, and a third terminal coupled to a corresponding second dataline. For example, pixel switch PW111 has a first terminal coupled topixel P111, a second terminal coupled to gate line G1, and a thirdterminal coupled to second data line SD11. Source driving circuit 304 isused for converting image data into a plurality of data voltages andenabling DI first data lines FD1-FDM, where M is a positive integer,each first data line of the M first data lines FD1-FDM corresponds to aplurality of data line switches, and each first data line ischarged/discharged according to corresponding data voltage, where eachdata line switch corresponds to a second data line and one of six switchenable lines SW1-SW6, and data line switches are N-type thin-filmtransistors or P-type thin-film transistors, but the present inventionis not limited to six switch enable lines SW1-SW6. For example, firstdata line FD1 corresponds to three data line switches DS11, DS12, DS13,first data line FD2 corresponds to three data line switches DS21, DS22,DS23, data line switches DS11 corresponds to second data line SD11 andswitch enable line SW1, data line switch DS12 corresponds to second dataline SD12 and switch enable line SW2, data line switch DS13 correspondsto second data line SD13 and switch enable line SW3, data line switchDS21 corresponds to second data line SD21 and switch enable line SW4,data line switch DS22 corresponds to second data line SD22 and switchenable line SW5, and data line switch DS23 corresponds to second dataline SD23 and switch enable line SW6. Additionally, each data lineswitch has a first terminal coupled to a corresponding first data line,a second terminal coupled to a corresponding switch enable line, and athird terminal coupled to a corresponding second data line. For example,data line switch DS11 has a first terminal coupled to first data lineFD1, a second terminal coupled to switch enable line SW1, and a thirdterminal coupled to second data line SD11. Gate driving circuit 306 isused for enabling N gate lines G1-GN, where N is a positive integer, twoneighboring gate lines have partially overlapping enable signals, andtwo neighboring pixel switches of each row of pixels in LCD panel 302turn on and turn off according to enable signals of two correspondinggate lines, respectively. For example, pixel switch PW111 turns on andturns off according to enable signal of gate line G1, and pixel switchPW221 turns on and turns off according to enable signal of gate line G2.Timing controller 308 is used for sequentially enabling a plurality ofswitch enable lines SW1-SW6.

As shown in FIG. 3B, in region T1, gate line G1 is enabled and switchenable lines SW1, SW2, SW3 are enabled sequentially, where enable signalof gate line G1 is as long as the sum of lengths of enable signals ofswitch enable lines SW1, SW2, SW3. However, the present invention is notlimited thereto, namely enable signal of gate line G1 may have lengthlonger than the sum of lengths of enable signals of switch enable linesSW1, SW2, SW3. Thus, when switch enable line SW1 and gate line G1 areboth enabled, first data line FD1 charges second data line SD11 throughturned on data line switch DS11 according to corresponding data voltage,and second data line SD11 charges pixel P111 through turned on pixelswitch PW111 according to corresponding data voltage. When switch enableline SW2 and gate line G1 are both enabled, first data line FD1 chargessecond data line SD12 through turned on data line switch DS12 accordingto corresponding data voltage, and second data line SD12 charges pixelP112 through turned on pixel switch PW112 according to correspondingdata voltage. When switch enable line SW3 and gate line G1 are bothenabled, first data line FD1 charges second data line SD13 throughturned on data line switch DS13 according to corresponding data voltage,and second data line SD13 charges pixel P113 through turned on pixelswitch PW113 according to corresponding data voltage. Likewise, inregion T2, operation of gate line G2, second data line FD2 and switchenable lines SW4, SW5, SW6 is similar to that of gate line G1, seconddata line FD1 and switch enable lines SW1, SW2, SW, and is not describedagain here. As shown in FIG. 3B, enable signal of gate line G1 continuesto region T2, so that pixel P111, pixel P112 and pixel P113 are allcharged continuously up to region T2, i.e. in the partially overlappingperiod (region T2) of enable signal of gate line G1 and enable signal ofgate line G2, pixel P111, pixel P112 and pixel P113 are chargedcontinuously. In this way, liquid crystal display 300 may have increasedpixel charging rate. Operation timings of remaining gate lines of liquidcrystal display 300 are the same as those of gate line G1 and gate lineG2, and are not described again here.

Please refer to FIG. 4, which is a diagram of liquid crystal display400. Liquid crystal display 400 comprises LCD panel 402, source drivingcircuit 404, gate driving circuit 406, and timing controller 408. Liquidcrystal display 400 differs from liquid crystal display 300 in that eachpixel switch of each row of pixels in LCD panel 402 turns on and turnsoff according to enable signal of gate line corresponding to each row ofpixels, and each two neighboring pixels of each column of pixels in LCDpanel 402 are charged/discharged according to corresponding datavoltages of two second data lines corresponding to each row of pixelsrespectively. For example, pixel P111, pixel P112 and pixel P113 turn onand turn off according to enable signal of gate line G1, and pixel P111and pixel P221 are charged/discharged according to data voltages ofsecond data line SD11 and second data line SD21. Operation principlesand timings of liquid crystal display 400 are similar to those of liquidcrystal display 300, and are not described again here.

Please refer to FIG. 5, which is a flowchart of a method ofcharging/discharging pixels of a liquid crystal display according to anembodiment. The method shown in FIG. 5 is illustrated with reference toliquid crystal display 300 of FIG. 3A, and comprises the followingsteps:

Step 502: Source driving circuit 304 converts image data into aplurality of data voltages;

Step 504: First data line FD1 is charged/discharged according to a datavoltage of a plurality of data voltages;

Step 506: Gate driving circuit 306 enables gate line G1 corresponding tofirst data line FD1 of a plurality of gate lines G1-GN;

Step 508: Timing controller 308 sequentially enables switch enable linesSW1-SW3 of switch enable lines SW1-SW6 corresponding to gate line G1;

Step 510: Turn on pixel switches PW111-PW113 corresponding to gate lineG1 according to enabled gate line G1;

Step 512: Sequentially turn on corresponding data line switchesDS11-DS13 according to sequentially enabled switch enable lines SW1-SW3;

Step 514: Data voltages sequentially charge/discharge correspondingsecond data lines SD11-SD13 through sequentially turned on data lineswitches DS11-DS13;

Step 516: Charged/discharged second data lines SD11-SD13 chargecorresponding pixels P111-P113 through turned on pixel switchesPW111-PW113.

In step 508, enable signal of gate line G1 is as long as the sum oflengths of enable signals of switch enable lines SW1, SW2, SW3. However,the present invention is not limited thereto, namely enable signal ofgate line G1 may be longer than the sum of lengths of enable signals ofswitch enable lines SW1, SW2, SW3. In step 514, data voltage on firstdata line FD1 sequentially charges/discharges second data linesSD11-SD13 through sequentially turned on data line switches DS11-DS13 .Thus, in step 516, charged/discharged second data lines SD11-SD13sequentially charge/discharge pixels P111-P113 through turned on pixelswitches PW111-PW113. Likewise, as shown in FIG. 3A, data voltage onfirst data line FD2 charges pixels P221-P223 according to steps shown inFIG. 5, where pixels P221-P223 correspond to gate line G2. Thus, in theembodiment of FIG. 5, pixels P111-P113 charged/discharged during enablesignal of gate line G1 are on the same row as pixels P221-P223charged/discharged during enable signal of G2. Additionally, second datalines SD11-SD13 continuously charge/discharge pixels P111-P113 throughturned on pixel switches PW111-PW113 during partially overlapping periodof enable signal of gate line G1 and enable signal of gate line G2.

Additionally, in another embodiment of FIG. 5 (corresponding to liquidcrystal display 400 of FIG. 4), data voltage on first data line FD2charges/discharges pixels P221-P223 according to the steps of FIG. 5,where pixels P221-P223 correspond to gate line G2. Thus, in anotherembodiment of FIG. 5, pixels P111-P113 charged/discharged during enablesignal of gate line G1 and pixels P221-P223 charged/discharged duringenable signal of gate line G2 are pixels of two neighboring rows.

In summary, liquid crystal displays and methods of charging/dischargingpixels of liquid crystal displays disclosed above utilize twoconsecutive, partially overlapping gate line enable signals andsequentially enabled switch enable lines to extend charging/dischargingtime of pixels. Thus, the embodiments increase pixel charging rate toimprove on the problem of the prior art of different charging ratesbetween pixels corresponding to the same first data line.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

What is claimed is:
 1. A liquid crystal display (LCD), comprising: anLCD panel comprising a plurality of pixels, wherein each pixel of theplurality of pixels is coupled to a corresponding pixel switch; a timingcontroller for enabling data line switches corresponding to 2X switchenable lines; a source driving circuit for converting image data into Mdata voltages for being sent to M first data lines respectively, whereinan Mi_(th) first data line of the M first data lines is coupled to Xsecond data lines through X data line switches, pixels corresponding tothe Mi_(th) first data line are charged or discharged according to anMi_(th) data voltage corresponding to the Mi_(th) first data line, an(Mi+1)_(th) first data line of the M first data lines is coupled to Xsecond data lines through X data line switches, pixels corresponding tothe (Mi+1)_(th) first data line charged or discharged according to an(Mi+1)_(th) data voltage corresponding to the (Mi+1)_(th) first dataline, an Xi_(th) data line switch of the X data line switches coupled tothe Mi_(th) first data line is coupled to an corresponding second dataline and an Xi_(th) switch enable line of the 2X switch enable lines,and an Xi′, data line switch of the X data line switches coupled to the(Mi+1)_(th) first data line is coupled to an corresponding second dataline and an (X+Xj)_(th) switch enable line of the 2X switch enablelines; and a gate driving circuit for enabling N gate lines; whereineach pixel of an Ni_(th) row of pixels coupled to X second data linescorresponding to the Mi_(th) first data line is coupled to an(2Ni−1)_(th) gate line of the N gate lines through a corresponding pixelswitch and located at an under side of the (2Ni−1)_(th) gate line and afirst side of a corresponding second data line, each pixel of anNj_(th), row of pixel coupled to X second lines corresponding to the(Mi+1)_(th) first data line is coupled to a (2Nj)_(th) gate line of theN gate lines through a corresponding pixel switch and located at anunder side of the (2Nj)_(th) gate line and a second side of acorresponding second data line, a kth second data line of X second datalines coupled to the (Mi+1)_(th) first data line is located between ak_(th) second data line and a (k+i)_(th) second data line of X seconddata lines coupled to the Mi_(th) first data line, enable signalsflowing on a gate line and a next gate line corresponding to the gateline are partially overlapping in the N gate lines, and M, N, Mi, Ni, X,Xi, Xj and k are positive integers.
 2. The liquid crystal display ofclaim 1, wherein duration of an enable signal flowing on each gate lineof the N gate lines is equal to a sum of durations of enable signalsflowing on the 2X switch enable lines.
 3. The liquid crystal display ofclaim 1, wherein duration of an enable signal flowing on each gate lineof the N gate lines is larger than a sum of durations of enable signalsflowing on the 2X switch enable lines.
 4. The liquid crystal display ofclaim 1, wherein a plurality of pixels corresponding to the gate linecontinue to be charged or discharged by a plurality of second data linescorresponding to the gate line when the enable signals flowing on thegate line and the enable signals flowing on the next gate line overlap.5. The liquid crystal display of claim 1, wherein each data line switchhas a first terminal coupled to a corresponding first data line, asecond terminal coupled to a corresponding switch enable line, and athird terminal coupled to a corresponding second data line.
 6. Theliquid crystal display of claim 1, wherein each pixel switch has a firstterminal coupled to a corresponding pixel, a second terminal coupled toa corresponding gate line, and a third terminal coupled to acorresponding second data line.
 7. A liquid crystal display (LCD),comprising: an LCD panel comprising a plurality of pixels arranged inrows; a timing controller having a plurality of switch enable lines andconfigured to enable data line switches; a source driving circuitconfigured to convert image data into data voltages and to control theplurality of pixels using the data voltages, the plurality of pixelsbeing coupled to the source driving circuit by having each of theplurality of pixels coupled to a second data line of a plurality ofsecond data lines, the data line switches coupling the plurality ofsecond data lines to a first data line of a plurality of first datalines, the plurality of first data lines being coupled to the sourcedriving circuit, a group of consecutive pixels of a row of pixels of theplurality of pixels being coupled to one first data line of theplurality of first data lines and the group of consecutive pixels of animmediately next row of pixels of the plurality of pixels being coupledto another one first data line of the plurality of first data lines; anda gate driving circuit configured to enable the plurality of pixels, theplurality of pixels receiving enable signals from a plurality of gatelines coupled to the gate driving circuit, the group of consecutivepixels of each row of pixels being coupled to a corresponding gate lineof the plurality of gate lines, wherein a first enable signal of theenable signals for the first gate line partially overlaps a secondenable signal of the enable signals for the second gate line so that aduration between a falling edge of the first enable signal for the firstgate line and a raising edge of the second enable signal for the secondgate line is substantially equal to a sum of durations of switch enablesignals being applied to switch enable lines, of the plurality of switchenable lines, configured to enable the data line switches coupling toonly the group of consecutive pixels connected to the second gate line.8. The liquid crystal display of claim 7, wherein duration of an enablesignal being applied to each gate line of the plurality of gate lines isequal to a sum of durations enable signals being applied to theplurality of switch enable lines.
 9. The liquid crystal display of claim7, wherein duration of an enable signal being applied to each gate lineof the plurality of gate lines is larger than a sum of durations ofenable signals being applied to the plurality of switch enable lines.10. The liquid crystal display of claim 7, wherein the row of pixelscorresponding to the gate line continue to be charged or discharged by aplurality of second data lines corresponding to the gate line when theenable signals being applied to the gate line overlap the enable signalsbeing applied to the immediately next gate line.
 11. The liquid crystaldisplay of claim 7, wherein each data line switch has a first terminalcoupled to a corresponding first data line, a second terminal coupled toa corresponding switch enable line, and a third terminal coupled to acorresponding second data line.
 12. The liquid crystal display of claim7, wherein each pixel switch has a first terminal coupled to acorresponding pixel, a second terminal coupled to a corresponding gateline, and a third terminal coupled to a corresponding second data line.